<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>synthesis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper{ width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table td.label { min-width: 100px; width: 8%;}
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\Gowin\Gowin_V1.9.8\IDE\ipcore\DVI_TX\data\dvi_tx_top.v<br>
D:\Gowin\Gowin_V1.9.8\IDE\ipcore\DVI_TX\data\rgb2dvi.vp<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">GowinSynthesis Version</td>
<td>GowinSynthesis V1.9.8</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV55PG484C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-55</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Oct 19 16:35:15 2021
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>DVI_TX_Top</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 27.910MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 27.910MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 27.910MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 27.910MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 27.910MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 27.910MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 27.910MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 27.910MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 27.910MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 27.910MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 27.910MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 27.910MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 44.391MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 44.391MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 44.391MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 44.391MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>38</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>34</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>30</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspTLVDS_OBUF</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>73</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFP</td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>70</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>213</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>29</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>50</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>134</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>68</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>68</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>IOLOGIC </b></td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOSER10</td>
<td>4</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>285(217 LUTs, 68 ALUs) / 54720</td>
<td>1%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>73 / 41997</td>
<td>1%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 41997</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>73 / 41997</td>
<td>1%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>0 / 140</td>
<td>0%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>I_rgb_clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>I_rgb_clk_ibuf/I </td>
</tr>
<tr>
<td>I_serial_clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>I_serial_clk_ibuf/I </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>I_rgb_clk</td>
<td>100.0(MHz)</td>
<td>120.1(MHz)</td>
<td>12</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.675</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.153</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_rgb_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>I_rgb_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_rgb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_rgb_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>77</td>
<td>I_rgb_clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/I3</td>
</tr>
<tr>
<td>2.495</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/F</td>
</tr>
<tr>
<td>2.732</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/I0</td>
</tr>
<tr>
<td>3.249</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/F</td>
</tr>
<tr>
<td>3.486</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/I0</td>
</tr>
<tr>
<td>4.003</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/F</td>
</tr>
<tr>
<td>4.240</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/I1</td>
</tr>
<tr>
<td>4.794</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/F</td>
</tr>
<tr>
<td>5.031</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I2</td>
</tr>
<tr>
<td>5.484</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F</td>
</tr>
<tr>
<td>5.721</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/I1</td>
</tr>
<tr>
<td>6.292</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/COUT</td>
</tr>
<tr>
<td>6.292</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/CIN</td>
</tr>
<tr>
<td>6.761</td>
<td>0.470</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/SUM</td>
</tr>
<tr>
<td>6.998</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n578_s6/I3</td>
</tr>
<tr>
<td>7.369</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n578_s6/F</td>
</tr>
<tr>
<td>7.606</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n578_s3/I0</td>
</tr>
<tr>
<td>8.123</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n578_s3/F</td>
</tr>
<tr>
<td>8.361</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n578_s1/I1</td>
</tr>
<tr>
<td>8.916</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n578_s1/F</td>
</tr>
<tr>
<td>9.153</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_rgb_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_rgb_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>77</td>
<td>I_rgb_clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>12</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.451, 65.753%; route: 2.607, 31.448%; tC2Q: 0.232, 2.799%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.730</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.097</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_rgb_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>I_rgb_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_rgb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_rgb_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>77</td>
<td>I_rgb_clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/I3</td>
</tr>
<tr>
<td>2.495</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/F</td>
</tr>
<tr>
<td>2.732</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/I0</td>
</tr>
<tr>
<td>3.249</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/F</td>
</tr>
<tr>
<td>3.486</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/I0</td>
</tr>
<tr>
<td>4.003</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/F</td>
</tr>
<tr>
<td>4.240</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/I1</td>
</tr>
<tr>
<td>4.794</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/F</td>
</tr>
<tr>
<td>5.031</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I2</td>
</tr>
<tr>
<td>5.484</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F</td>
</tr>
<tr>
<td>5.721</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3/I1</td>
</tr>
<tr>
<td>6.276</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3/SUM</td>
</tr>
<tr>
<td>6.513</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n579_s3/I1</td>
</tr>
<tr>
<td>7.068</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n579_s3/F</td>
</tr>
<tr>
<td>7.305</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n579_s1/I1</td>
</tr>
<tr>
<td>7.860</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n579_s1/F</td>
</tr>
<tr>
<td>8.097</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_rgb_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_rgb_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>77</td>
<td>I_rgb_clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.633, 64.036%; route: 2.370, 32.757%; tC2Q: 0.232, 3.207%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.973</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.854</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_rgb_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>I_rgb_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_rgb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_rgb_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>77</td>
<td>I_rgb_clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>17</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s21/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s21/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/I0</td>
</tr>
<tr>
<td>2.641</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/F</td>
</tr>
<tr>
<td>2.878</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I1</td>
</tr>
<tr>
<td>3.433</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F</td>
</tr>
<tr>
<td>3.670</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15/I0</td>
</tr>
<tr>
<td>4.187</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15/F</td>
</tr>
<tr>
<td>4.424</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/I1</td>
</tr>
<tr>
<td>4.994</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/COUT</td>
</tr>
<tr>
<td>4.994</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4/CIN</td>
</tr>
<tr>
<td>5.464</td>
<td>0.470</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4/SUM</td>
</tr>
<tr>
<td>5.701</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/n578_s5/I3</td>
</tr>
<tr>
<td>6.071</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/n578_s5/F</td>
</tr>
<tr>
<td>6.308</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/n578_s3/I0</td>
</tr>
<tr>
<td>6.826</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/n578_s3/F</td>
</tr>
<tr>
<td>7.063</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/n578_s1/I1</td>
</tr>
<tr>
<td>7.617</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/n578_s1/F</td>
</tr>
<tr>
<td>7.854</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_rgb_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_rgb_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>77</td>
<td>I_rgb_clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.627, 66.176%; route: 2.133, 30.506%; tC2Q: 0.232, 3.318%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.999</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.829</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_rgb_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>I_rgb_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_rgb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_rgb_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>77</td>
<td>I_rgb_clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>7</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/n658_s3/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/n658_s3/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s21/I1</td>
</tr>
<tr>
<td>2.679</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s21/F</td>
</tr>
<tr>
<td>2.916</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/I1</td>
</tr>
<tr>
<td>3.471</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/F</td>
</tr>
<tr>
<td>3.708</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s19/I3</td>
</tr>
<tr>
<td>4.079</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s19/F</td>
</tr>
<tr>
<td>4.316</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5/I1</td>
</tr>
<tr>
<td>4.886</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5/COUT</td>
</tr>
<tr>
<td>4.886</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/CIN</td>
</tr>
<tr>
<td>5.356</td>
<td>0.470</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/SUM</td>
</tr>
<tr>
<td>5.593</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/n578_s5/I2</td>
</tr>
<tr>
<td>6.046</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/n578_s5/F</td>
</tr>
<tr>
<td>6.283</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/n578_s3/I0</td>
</tr>
<tr>
<td>6.800</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/n578_s3/F</td>
</tr>
<tr>
<td>7.037</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/n578_s1/I1</td>
</tr>
<tr>
<td>7.592</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/n578_s1/F</td>
</tr>
<tr>
<td>7.829</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_rgb_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_rgb_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>77</td>
<td>I_rgb_clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.601, 66.050%; route: 2.133, 30.620%; tC2Q: 0.232, 3.330%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.118</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.710</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_rgb_clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>I_rgb_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_rgb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_rgb_clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>77</td>
<td>I_rgb_clk_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/I3</td>
</tr>
<tr>
<td>2.495</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/F</td>
</tr>
<tr>
<td>2.732</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/I0</td>
</tr>
<tr>
<td>3.249</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/F</td>
</tr>
<tr>
<td>3.486</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1/I1</td>
</tr>
<tr>
<td>4.041</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1/F</td>
</tr>
<tr>
<td>4.278</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n628_s1/I1</td>
</tr>
<tr>
<td>4.832</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n628_s1/F</td>
</tr>
<tr>
<td>5.069</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n628_s3/I0</td>
</tr>
<tr>
<td>5.587</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n628_s3/F</td>
</tr>
<tr>
<td>5.824</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n654_s1/I1</td>
</tr>
<tr>
<td>6.378</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n654_s1/F</td>
</tr>
<tr>
<td>6.615</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n654_s0/I0</td>
</tr>
<tr>
<td>6.719</td>
<td>0.103</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n654_s0/O</td>
</tr>
<tr>
<td>6.956</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n664_s0/I0</td>
</tr>
<tr>
<td>7.473</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/n664_s0/F</td>
</tr>
<tr>
<td>7.710</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>I_rgb_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>I_rgb_clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>77</td>
<td>I_rgb_clk_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.245, 61.998%; route: 2.370, 34.614%; tC2Q: 0.232, 3.388%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>
